The present invention relates to reduced-size capacitor structures for integrated circuits.
In integrated circuit technology, reducing the size of circuit structures is a general goal as it allows higher integration density, faster circuit operation and less power consumption. One type of widely-used circuit structure is a capacitor, which in principle is composed of two electrodes separated and insulated from each other by a dielectric layer. Reducing the thickness of the dielectric layer increases the capacitance of the capacitor; so does increasing the capacitor""s effective electrode area. Because avoidance of undesired breakdown and tunneling effects sets a limit on the minimum thickness of the dielectric layer, reducing the chip area occupied by the capacitor without decreasing the effective electrode area is crucial to achieving desired capacitance values while attaining higher levels of circuit integration. Therefore, it is highly desirable to have an innovative circuit structure that allows formation of capacitors of reduced size, yet high capacitance.
The present invention provides a high-performance capacitive electrode structure that supports down-scaling of integrated circuits and allows die size reduction. The electrode structure is fabricated on a substrate and comprises a first electrode and a second electrode. The first electrode is formed by a diffusion region in the substrate, while the second electrode is formed by a conductive layer that is deposited on an insulating layer formed atop the diffusion region. A plurality of recesses are formed in the first electrode on an upper surface thereof, and a lower surface of the second electrode substantially follows a contour of these recesses. In this way, the effective electrode area of the capacitive electrode structure is enhanced without increasing its overall size. In a preferred embodiments the recesses, which can be formed of, for example, holes or grooves, are formed concurrently with isolation trenches in the substrate that are subsequently filled with a field oxide for the purpose of isolating adjacent circuit elements from each other.